Job Description

Physical Design Flow and Methodology Engineer link Copy link corporate_fare Google place Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Apply link Copy link Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with EDA tool workflows in a semiconductor environment. Experience developing automated physical design workflows from RTL to GDS, utilizing Tcl, Python, or Perl. Experience with physical design implementation and convergence at the block and subsystem levels. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience leading physical design end-to-end execution from RTL to GDS. Experience in extraction of design parameters, quality of results (QoR), and analyzing trends. Experience in documentation, training, and support to increase end user productivity. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be a part of the chip implementation team developing flows and methodologies for workflow automation, data management, metric collection and dashboarding for physical design Electronic Design Automation (EDA) tools within the Google Compute Engine environment. You will survey industry trends, perform technical evaluations of vendors, provide recommendations and employ best practices. Your work will streamline ASIC physical design workflows, make our team of physical design engineers more efficient, and help ensure high quality of results for ASIC tapeouts. You will work with industry-standard physical design EDA tools and RTL To GDS CAD flows such as place and route, EM/IR, static timing, etc. You will also possess a good command of common scripting languages. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Architect and implement next generation Physical Design EDA CAD tool workflows for ASIC development. Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes. Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools. Own the physical design of blocks and subsystems end-to-end. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr Google Inc.

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